issi ddr2 sdram design considerations gu ide introduction this is a general board design considerations guideline for issi ddr2 sdram, especially for point to point application s . c hipset comp anies may have their own application notes for designing using ddr2 dram . issi recommends following the chipset companys guidelines first. pcb layout guidelines 50 C 60 impedance (zo) is recommended for all traces. fr - 4 is commonly used for the dielectric material. the board thickness and trace width and thickness should be adjusted to match the impedance. trace lengths are also influential, and they should be dete rmined by simulation for each signal group and verified in test . in general, issi recommends the minimum rule s for trace s in the board as shown below for the minimization of crosstalk . th ese rule s are based on the assumption of a signal slew rate of 1v/1ns. in s lower applications, cross - talk generally is not a factor, and closer spacing may be allowed. 1. signals from the same net group should be routed on the same layer. 2. signals from byte group, such as dqs, dm and 8 bits of dq, mus t be routed in the same layer 3. t he deviation of signal propagation delay is dependent on the timing budget on the application. the following values in the table are good examples at the start of a design. signals on net maximum deviation of signal propagation difference. maximum deviation of trace length . all data, address and command signals must be followed within this variation. 50ps 6.635mm(261mil) between ck and ck#. between dqsn and dqs#n 2 ps 0. 254 mm (10mil) between one clock pair and another clock pair , eg) ck/ck# and dqsn/dqs#n 5 ps 0.635mm (25mil) between signals within byte group(dqs,dm,8bits of dq) 10ps 1.270mm(50mil) 4. minimum t race width is 0.13mm ( 5mil). 5. intranet spacing, the distance between two adjacent traces within a net, is 0.2mm ( 7mil). 6. internet spacing, the distance between the two outermost signals of different signal group is 15mil. the s ame rule applies between one clock pair and another clock pa ir. 7. differential clocks should be routed in parallel and keep the trace length short. 8. differential clocks must be routed on the same layer and placed on an internal layer minimize the noise. 9. keep the internet spacing rule between cke and ck/ck#
v ref control setup and hold time margin could be reduced if vref has noise. vref integrity should be provided by the user to optimize noise margin in the system. the vref level is expected to track variations in vddq , and the peak - to - peak noise should be met w ith specification: 1. 1k?1%/1k?1%/ from vddq power panel 2. place a 0.1uf capacitor between vref and vddq 3. place a 0.1uf capacitor between vref and vssq 4. vref should have a minimum trace to reduce inductance 5. vref should keep a distance from other signals to reduce the potential of a decoupling effect emi and t ermination the ddr2 sdram offers full drive strength and reduced drive strength, as recommended by jedec. they are controlled by emrs setting, during initialization. the full drive has an output impedance of about 18 and the reduced drive has an output impedance of about 40. selecting the drive strength should be based on the simulation result. ddr2 sdram offers odt features for dm, dqs and dq s pins. with a short trace length ( less than 5cm ) , it may not required. matching impedance by using a serial resistor can also improve the performance , but odt control is generally recommended for better signal integrity. if a serial resistor is used, 10 - 33 ? serial resistor can be used and located to the middle portion of the trace. for the command and address inputs, typically, 10~33 ? serial resistor termination is used and closely located to the transmitting device , if it is required. for clock inputs, issi doesnt recommend any termination, except adding 100~120 ? between differential clocks. the t race needs to be as short as pos sible to reduce noise. if any signal trace is longer than 5cm , r tt to v tt will be recommended. power s u pply and decoupling capacitors in most cases , to specifically decouple the dram, it is popular and effective to use one or two 10uf or 4.7uf bulk capacitor s near ldo and several 0.1uf decoupling capacitors close to the ddr2 . however, this recommendation may not be sufficient to cover the wide variety of applications using ddr2 today . because of this , issi recommends comprehensive board simulation s to ensure the optimal power supply condition s in ddr2 memory applications.
ddr2 datasheet s specify vdd, vddq , and vddl condition as 1.8v+ - 100mv. this specification is a dc condition for the device that assumes ideal voltage conditions without current defi ciencies . vdd and vddq often share the same power plane in the board, which can result in level shifts on vdd. this condition is caused by ddr2 high frequency i/o switching (vddq) which consume s a large amount of current vs vdd requirements . i n typical ddr2 applications , most volta ge variation s are caused by current limitation s, which are the result dynamic power requirements that change over the course of the various operational modes of the dram . the f ollowing chart s illustrate current deficiencies and voltage drop (s) caused by a change in the operating mode from standby to active . major factors that contribute to current deficiencies in ddr2 applications are inductances and power supply design methodologies. inductances are resistive to current changes, acting as a constrain t to the amount of instantaneous current that is available when operating modes change. w hen the device transition s from standby to active mode , the current demand incr eases rapidly ( fig 1 - green trace ) . if a board design has excessive supply path inductances, this sudden demand increase can easily exceed the capability of the power supply to provide the needed current. the current deficienc y resulting from the high inductance is highlighted by the red t riangle. the lack of current is visible in the voltage drop ( fig 1 - yellow trace ) until the power supply can provide enough current to meet the active p ower requirements . because of this potential phenomenon, supply path inductances should be minimized and v o ltage drops should not exceed 5 0mv ( duration must be < 2 0us ) , n or should they exceed 70mv (duration must be < 10us). [fig 1. ] voltage dip caused by inductive supply paths resulting in vdd/vddq current deficiencies . power supply responds immediately after device consume the current 220ma 60ma operating period standby period
power supply designs can also contribute to current deficiencies , if the response time of the supply is too slow to adjust to the dynamic needs of the power conditions. these dynamic conditions include the switching of the odt function, refresh cycles, read cycles and write cycles. the following plot (fig 2 ) illustrates that a s the operating modes change , the power supply cant adjust its curren t source fast enough to satisfy the increased active power requirement . this produces a similar voltage drop to the inductive example (fig 1) until the power supply sense s the voltage deficiency and responds with ad ditional current to support the active mode . [fig 2.] vo ltage dip due to supply design causing the current deficiency. active mode standby current supply doesn t change even after operating mode is changed.
in fig 3, a large capacitor is used to provide additional current when the operating mode is switched from standby to active mode. t he additional current source ( large capacitor ) reduces the slope of the power supply vo ltage drop, but lengthens the reaction time of the supply to the increased active power requirements . while t he additional capacitance provides a short term solution it does not resolve the overall power supply deficiency which requires further investigation. [fig 3. ] additional capacitance reduces the voltage dip but the supplies reaction time is slower . in the examples above , dynamic current deficiencies resulting from ddr2 operational mode changes can be reduced with optimal power supply selection, low inductance paths and careful selection decoupling capacitors to minimize the response time s during peak current demand . in ddr2 applications , issi recommends that power supply dips should not exceed 50mv ( duration must be less than 20us , nor should they exceed 70mv (duration must be less than 10us). land pattern we recommend the design f ollow ipc - sm - 782a, whereby one should keep the size of land pattern to be equal to 80% of the ball size of bga. active mode standby
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